In the monolithic integrated circuit technology, it is usually necessary to isolate various active and passive devices from one another in the integrated circuit structure. These devices have been isolated by back-biasing PN junctions, partial dielectric isolation and complete dielectric isolation. The dielectric materials used have been silicon dioxide, glass, etc. The preferred isolation for these active devices and circuits is complete dielectric isolation. However, such structures have been very difficult to fabricate.
One form of complete dielectric isolation is taught by the J. G. Kren et al., U.S. Pat. No. 3,419,956 and P. P. Castrucci et al., U.S. Pat. No. 3,575,740, both of which are assigned to the present assignee. The method of manufacturing this form of dielectric isolation involves the formation of a grid of channels in a monolithic silicon semiconductor wafer. A layer of silicon dioxide or other dielectric material is then formed on the surface of the wafer. Polycrystalline silicon is then grown on top of the silicon dioxide or other dielectric material in a substantial thickness. The monolithic silicon is then etched or lapped away until the grid of channels which are silicon dioxide or other dielectric material is reached. The remaining portions of the monocrystalline silicon wafer are now isolated from one another by the grid of dielectric material. Semiconductor devices and circuits can now be formed in the isolated monocrystalline silicon regions.
The A. K. Hochberg, U.S. Pat. No. 3,966,577 describes a variation of the above described patents for forming dielectric isolated semiconductor regions especially adapted for the construction of an integrated circuit on an epitaxial wafer. A layer of silicon dioxide is grown on the back-side of the wafer and a layer of polycrystalline silicon is deposited onto the silicon dioxide layer. An aluminum oxide mask is formed defining a plurality of grooves around active semiconductor regions within the epitaxial silicon layer. The grooves are formed by a sputter etching process. Silicon dioxide is thermally grown within each of the grooves exposed by the sputter etching process to dielectrically isolate the active semiconductor regions after which semiconductor devices may be formed in each of the active semiconductor regions.
A still further process for forming complete dielectric isolation is described in the H. B. Pogge, U.S. Pat. No. 4,104,090 which is assigned to the present assignee. This process utilizes an anodized porous silicon technique to form the dielectric isolation on one side of the semiconductor device. The starting silicon wafer is typically predominantly P with a P+ layer thereon. A P or N layer is deposited over the P+ layer such as by epitaxial growth. The surface of the silicon wafer is oxidized and suitable openings are formed using conventional lithography. Openings are formed in the silicon dioxide layer to define the regions to be etched in the epitaxial silicon layer down to the P+ layer. Reactive ion etching is accomplished at least down to the P+ region. The structure is then subjected to the anodic etching technique which preferentially attacks the P+ layer to form a porous silicon throughout the P+ layer. The structure is then placed in a thermal oxidation ambient until the porous silicon layer has been fully oxidized to silicon dioxide. The openings through the surface silicon layer are filled up by a silicon dioxide or like insulator to isolate the P or N monocrystalline surface regions from one another.
The J. A. Bondur et al. U.S. Pat. No. 4,104,086 assigned to the same assignee as the present invention describes a method for forming partial dielectric isolation with filled grooves or depressions of dielectric material. In the preferred embodiment of this invention, it was necessary to reactive ion etch the grooves or depressions through a N+ region which was eventually to become the subcollector region for bipolar devices. This presented difficulty because the N+ region would undercut the portion of the monocrystalline material above the N+ region during certain reactive ion etching conditions. This was undesirable in the context of this invention. A subsequent N. G. Anantha et al. U.S. Pat. No. 4,196,440 assigned to the same assignee as the present invention found this undercutting in the N+ layer an advantage and utilized it as partial isolation for a lateral PNP or NPN device.